<p style="font-family:"><b><strong style="color:rgb(0,0,0);font-size:13pt;white-space:pre-wrap;">About Positron AI</strong></b></p><p style="font-family:">Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.</p><p style="font-family:"><b><strong style="color:rgb(0,0,0);font-size:13pt;white-space:pre-wrap;">Role Overview</strong></b></p><p style="font-family:">Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.</p><p style="font-family:"><b><strong style="color:rgb(0,0,0);font-size:13pt;white-space:pre-wrap;">Key Responsibilities</strong></b></p><p style="font-family:"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Own the Positron DFT strategy</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.38;letter-spacing:0.25px;">Define and maintain the DFT architecture for Asimov and future ASIC generations.</li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.38;letter-spacing:0.25px;">Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives.</li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.38;letter-spacing:0.25px;">Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization.</li></ul><p style="font-family:"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Hands-on DFT implementation</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.38;letter-spacing:0.25px;">Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features.</li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.38;letter-spacing:0.25px;">Integrate DFT into internally developed RTL.</li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.