<p><span style="color: #121317">At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams. </span></p><p><span style="color: #121317">Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.<br /><br /></span><strong><span style="color: #121317">Key Responsibilities</span></strong><span style="color: #121317"><br /><br /></span><strong><span style="color: #121317">Block-Level Execution &amp; Convergence Engineering (90%)</span></strong></p><ul><li><p><strong><span style="color: #121317">End-to-End Testbench Ownership: </span></strong><span style="color: #121317">Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).</span></p></li><li><p><strong><span style="color: #121317">Datapath &amp; Arithmetic Verification:</span></strong><span style="color: #121317"> Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.</span></p></li><li><p><strong><span style="color: #121317">Proof Convergence Management:</span></strong><span style="color: #121317"> Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).</span></p></li><li><p><strong><span style="color: #121317">RISC-V Vector Compliance:</span></strong><span style="color: #121317"> Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.</span></p></li><li><p><strong><span style="color: #121317">Simulation Partnership:</span></strong><span style="color: #121317"> Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.</span></p></li></ul><p><strong><span style="color: #121317">Embedded Mentorship &amp; Best Practices (10%)</span></strong></p><ul><li><p><strong><span style="color: #121317">Formal-Friendly Design:</span></strong><span style="color: #121317"> Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and s